It is known in the semiconductor art that figures of merit may be used to describe the performance of a semiconductor device. One figure of merit of particular interest is defined as the numerical ratio between the emitter periphery (EP) and the base area (BA). By increasing the figure of merit, a device demonstrates improved current handling capability. Thus, a device is able to handle high power with low parasitic capacitance. In addition, such a device is highly suitable for high frequency applications (for example, at radio frequencies).
One way of increasing a device's figure of merit is by decreasing the "pitch" or spacing between repetitive patterns, i.e.-emitters. Due to the fact that integrated circuits typically have a planar structure, current that flows from the emitter to the collector typically travels parallel to the surface of the wafer after being transported vertically through the base. This current then flows upward towards a contact located on the wafer surface. Due to the significant resistivity of current-flow paths within the device, parasitic series resistances exist.
One such parasitic resistance is the so-called intrinsic base region (R.sub.BB). This resistance is caused by the path length between the base contact and the edge of the injecting emitter region and is related to base sheet resistance. Thus, by decreasing the pitch, or spacing between emitters, the length of the aforementioned path is decreased, resulting in a decreased parasitic resistance in that region.
The base area of a device may be readily decreased using appropriate photolithographic processes. However, current photolithographic processes are unable to produce device features smaller than 1 micron.
Although a reduced base area results in an increased figure of merit, a base area which is too small may lead to poor device performance. In particular, the spacings from base contact to emitter edge are large enough to allow a small amount of depletion so that proper device operation is obtained. Furthermore, if the spacing in selected portions of the device reaches zero, a short may occur, causing the device to become completely inoperative.
As an alternative to varying the distances in the intrinsic base region, some investigators have attempted to reduce the parasitic resistance of this region by selectively adding dopants to this region. This has been done in order to increase this region's conductivity. However, if the intrinsic base is doped too heavily a low emitter-base breakdown voltage may result, since this breakdown is a strong function of the high resistivity side of the junction, in this case, the base.